Nonvolatile semiconductor memory devices represented by flash memories are excellent in mobility and impact resistance and electrically bulk-erasable. Therefore, demand for the nonvolatile semiconductor memory devices as files of small-sized mobile information equipment such as a mobile personal computer, a digital still camera, and a digital video camera suddenly expand.
To expand the market of the nonvolatile semiconductor memory devices, it is essential to reduce cost by reducing an area of memory cells per bit. To this end, various techniques for storing data of two bits in one memory cell have been proposed.
Among these techniques, there is known one for injecting charges into discrete traps in a silicon nitride film, as disclosed in, for example, Patent Documents 1 (U.S. Pat. No. 6,011,725) and 2 (U.S. Pat. No. 5,966,603).
As shown in, for example, FIG. 85, a memory cell of this type comprises a p-type well 102 in a silicon substrate 101, source/drain diffusion layers 103 and 103′ in the well 102, a silicon nitride film 111 which is a charge injected film, a control gate 109, a silicon oxide film 105 which isolates the p-type well 102 from the silicon nitride film 111, and a silicon oxide film 108 which isolates the control gate 109 from the silicon nitride film 111. The control gates 109 of respective memory cells are connected to one another in a row direction to constitute word lines, respectively. The source/drain diffusion layers 103 and 103′ are shared between adjacent memory cells. Reference numeral 104 denotes an isolation region.
The memory cell stated above has a silicon oxide film (SiO2)/silicon nitride film (SiN)/silicon oxide film (SiO2) or so-called ONO film serving as a gate insulator film of a MOS (Metal Oxide Semiconductor) transistor. Therefore, the semiconductor memory device including these memory cells is referred to as “MONOS nonvolatile semiconductor memory device”.
According to the Patent Documents 1 and 2, channel hot electron injection is conducted for programming so as to store two bits in one memory cell, and electrons are injected into traps in the silicon nitride film 111 on both end portions of the sources 103 and 103′ according to voltage bias conditions.
First, to inject electrons into the silicon nitride film 111 on the end portion of the source 103′, independent positive voltages are biased to the word line (control gate) 109 and the drain 103′, respectively and voltages of the p-type well 102 and the source 103 are set at 0V, as shown in FIG. 86. As a result, hot electrons are generated in a channel on the end portion of the drain 103′, and the electrons are injected into the silicon nitride film 111 (a portion A in FIG. 86) on the end portion of the drain 103′.
Next, to inject electrons into the silicon nitride film 111 (a portion B in FIG. 87) on an end portion of the source 103, independent positive voltages are biased to the word line 109 and the source 103, respectively and voltages of the p-type well 102 and the drain 103′ are set at 0V, as shown in FIG. 87.
During reading, the source/drain diffusion layers 103 and 103′ are biased oppositely to those during programming so as to detect the injected electrons with high sensitivity, as shown in FIGS. 88 and 89.
As will be described later, a nonvolatile semiconductor memory device that secures a quantity of captured charges is disclosed in, for example, Patent Document 3 (Japanese Patent Application Laid-open No. 5-75133).